HALF ADDER: Structural Model: module hlfaddr(i1, i2, s, c); input i1; input i2; output s; output c; xor(s,i1,i2); and(c,i1,i2); endmodule Data Flow Model: module hlfaddr(i1, i2, s, c); input i1; input i2; output s; output c; assign s=i1^i2; assign c=i1&i2; endmodule FULL ADDER: Structural Model: module fulladdr(a, b, cin, s, cout); input a; input b; input cin; output s; output cout; wire s1,c1,c2; xor n1(s1,a,b); and n2(c1,a,b); xor n3(s,s1,cin); and n4(c2,s1,cin); or n5(cout,c1,c2); endmodule Data Flow Model: module fulladdr(a, b, cin, s, cout); input a; input b; input cin; output reg s; output reg cout; always@(a or b or cin) begin s=a^b^cin; cout=a&b|(a^b)&cin; end endmodule HALF SUBTRACTOR: Structural Model: module halfsub(i1, i2, d, b); input i1; input i2; output d; output b; xor(d,i1,i2); and(b,~i1,i2); endmodule Data Flow Model: m